TY - GEN
T1 - An approach to LUT based multiplier for short word length DSP systems
AU - Memon, Tayab D.
AU - Pathan, Aneela
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/6/4
Y1 - 2018/6/4
N2 - Short Word Length (SWL) DSP systems offer good performance as they process less data-typically up to three bits. Short Word Length systems may be designed using the FPGAs. FPGAs come with many built-in primitives like Look-up tables, Flip-flops, additional Carry logic, Memories and DSP elements. All these primitives give alternative approaches for FPGA based system design. This paper presents a way to use the Look-up tables to design three bit (3×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems. Besides, the feasibility of using Block ram and DSP elements for Short Word Length DSP system (multiplier) is also carried out as an alternative implementation approach. Result suggests the proposed way be the better one when compared with other two implementations.
AB - Short Word Length (SWL) DSP systems offer good performance as they process less data-typically up to three bits. Short Word Length systems may be designed using the FPGAs. FPGAs come with many built-in primitives like Look-up tables, Flip-flops, additional Carry logic, Memories and DSP elements. All these primitives give alternative approaches for FPGA based system design. This paper presents a way to use the Look-up tables to design three bit (3×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems. Besides, the feasibility of using Block ram and DSP elements for Short Word Length DSP system (multiplier) is also carried out as an alternative implementation approach. Result suggests the proposed way be the better one when compared with other two implementations.
KW - Built-in Core
KW - Combinational Logic Blocks
KW - FPGA
KW - Multiplier
UR - http://www.scopus.com/inward/record.url?scp=85049329321&partnerID=8YFLogxK
U2 - 10.1109/ICSIGSYS.2018.8372772
DO - 10.1109/ICSIGSYS.2018.8372772
M3 - Conference contribution
AN - SCOPUS:85049329321
T3 - 2018 International Conference on Signals and Systems, ICSigSys 2018 - Proceedings
SP - 276
EP - 280
BT - 2018 International Conference on Signals and Systems, ICSigSys 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd International Conference on Signals and Systems, ICSigSys 2018
Y2 - 1 May 2018 through 3 May 2018
ER -