An approach to LUT based multiplier for short word length DSP systems

Tayab D. Memon, Aneela Pathan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)

Abstract

Short Word Length (SWL) DSP systems offer good performance as they process less data-typically up to three bits. Short Word Length systems may be designed using the FPGAs. FPGAs come with many built-in primitives like Look-up tables, Flip-flops, additional Carry logic, Memories and DSP elements. All these primitives give alternative approaches for FPGA based system design. This paper presents a way to use the Look-up tables to design three bit (3×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems. Besides, the feasibility of using Block ram and DSP elements for Short Word Length DSP system (multiplier) is also carried out as an alternative implementation approach. Result suggests the proposed way be the better one when compared with other two implementations.

Original languageEnglish
Title of host publication2018 International Conference on Signals and Systems, ICSigSys 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages276-280
Number of pages5
ISBN (Electronic)9781538656891
DOIs
Publication statusPublished - 4 Jun 2018
Externally publishedYes
Event2nd International Conference on Signals and Systems, ICSigSys 2018 - Bali, Indonesia
Duration: 1 May 20183 May 2018

Publication series

Name2018 International Conference on Signals and Systems, ICSigSys 2018 - Proceedings

Conference

Conference2nd International Conference on Signals and Systems, ICSigSys 2018
Country/TerritoryIndonesia
CityBali
Period1/05/183/05/18

Keywords

  • Built-in Core
  • Combinational Logic Blocks
  • FPGA
  • Multiplier

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