Shift and add is conventional multiplication technique used at most, due to its simplest architecture. This simplicity becomes the bottleneck, when its hardware implementation takes more resources, when implemented on FPGAs. Though FPGA is, taken as an efficient implementation tool, but limited resources are the design hurdle observed many times. Optimizations is the way, opt, to design large circuits, especially whole system on chip (SOC), or network on chip (NOC) on this device. So many methods of multiplier optimization are found with some modifications in conventional methods along their implementation and testability on FPGA. In this paper, implementation of fixed point finite length 3×3 unsigned integer shift and add multiplier is shown, by introducing some changes in procedure. The modified version results in less resource utilizations in terms of Lookup Tables (LUTs) and produce less delay, due to less levels of logics, compared with conventional method.