Analysis and design of a ternary FIR filter using sigma delta modulation

Tayab D. Memon, Paul Beckett, Zahir M. Hussain

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)

Abstract

We present the analysis and design of a FIR filter with balanced ternary coefficients (i.e., -1, 0, +1) suitable for FPGA implementation. The ternary filter taps were generated using a ΣΔM process in MATLAB® and the filter implemented in VHDL. An efficient fast adder structure accumulates the partial multiplication products. Two alternative implementations in 2's complement and redundant binary signed digit representations are compared on a range of commercial FPGA devices for both pipelined and nonpipelined organizations. Using a high performance device, the filter can operate at clock rates of more than 400MHz.

Original languageEnglish
Title of host publicationINMIC 2009 - 2009 IEEE 13th International Multitopic Conference
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 IEEE 13th International Multitopic Conference, INMIC 2009 - Islamabad, Pakistan
Duration: 14 Dec 200915 Dec 2009

Publication series

NameINMIC 2009 - 2009 IEEE 13th International Multitopic Conference

Conference

Conference2009 IEEE 13th International Multitopic Conference, INMIC 2009
Country/TerritoryPakistan
CityIslamabad
Period14/12/0915/12/09

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