TY - GEN
T1 - Analysis and design of a ternary FIR filter using sigma delta modulation
AU - Memon, Tayab D.
AU - Beckett, Paul
AU - Hussain, Zahir M.
PY - 2009
Y1 - 2009
N2 - We present the analysis and design of a FIR filter with balanced ternary coefficients (i.e., -1, 0, +1) suitable for FPGA implementation. The ternary filter taps were generated using a ΣΔM process in MATLAB® and the filter implemented in VHDL. An efficient fast adder structure accumulates the partial multiplication products. Two alternative implementations in 2's complement and redundant binary signed digit representations are compared on a range of commercial FPGA devices for both pipelined and nonpipelined organizations. Using a high performance device, the filter can operate at clock rates of more than 400MHz.
AB - We present the analysis and design of a FIR filter with balanced ternary coefficients (i.e., -1, 0, +1) suitable for FPGA implementation. The ternary filter taps were generated using a ΣΔM process in MATLAB® and the filter implemented in VHDL. An efficient fast adder structure accumulates the partial multiplication products. Two alternative implementations in 2's complement and redundant binary signed digit representations are compared on a range of commercial FPGA devices for both pipelined and nonpipelined organizations. Using a high performance device, the filter can operate at clock rates of more than 400MHz.
UR - http://www.scopus.com/inward/record.url?scp=77950387317&partnerID=8YFLogxK
U2 - 10.1109/INMIC.2009.5383079
DO - 10.1109/INMIC.2009.5383079
M3 - Conference contribution
AN - SCOPUS:77950387317
SN - 9781424448722
T3 - INMIC 2009 - 2009 IEEE 13th International Multitopic Conference
BT - INMIC 2009 - 2009 IEEE 13th International Multitopic Conference
T2 - 2009 IEEE 13th International Multitopic Conference, INMIC 2009
Y2 - 14 December 2009 through 15 December 2009
ER -