FPGA based performance analysis of multiplier policies for FIR filter

Aneela Pathan; Tayab D. Memon; Sharmeen Keerio; Imtiaz Hussain Kalwar

doi:10.1109/ICAEES.2016.7888001

FPGA based performance analysis of multiplier policies for FIR filter

Aneela Pathan, Tayab D. Memon, Sharmeen Keerio, Imtiaz Hussain Kalwar

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.

Original language	English
Title of host publication	2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
Editors	Rosdiadee Nordin, Mohd Fais Mansor, Mahamod Ismail
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	17-20
Number of pages	4
ISBN (Electronic)	9781509028894
DOIs	https://doi.org/10.1109/ICAEES.2016.7888001
Publication status	Published - 27 Mar 2017
Externally published	Yes
Event	2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 - Putrajaya, Malaysia Duration: 14 Nov 2016 → 16 Nov 2016

Publication series

Name	2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016

Conference

Conference	2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
Country/Territory	Malaysia
City	Putrajaya
Period	14/11/16 → 16/11/16

Keywords

Booth Algorithm
FPGA
Multiplier Policies
Wallace Tree

Access to Document

10.1109/ICAEES.2016.7888001

Cite this

Pathan, A., Memon, T. D., Keerio, S., & Kalwar, I. H. (2017). FPGA based performance analysis of multiplier policies for FIR filter. In R. Nordin, M. F. Mansor, & M. Ismail (Eds.), 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 (pp. 17-20). [7888001] (2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICAEES.2016.7888001

Pathan, Aneela ; Memon, Tayab D. ; Keerio, Sharmeen et al. / FPGA based performance analysis of multiplier policies for FIR filter. 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. editor / Rosdiadee Nordin ; Mohd Fais Mansor ; Mahamod Ismail. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 17-20 (2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016).

@inproceedings{da511af15035469db6de04cd714f5661,

title = "FPGA based performance analysis of multiplier policies for FIR filter",

abstract = "In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.",

keywords = "Booth Algorithm, FPGA, Multiplier Policies, Wallace Tree",

author = "Aneela Pathan and Memon, {Tayab D.} and Sharmeen Keerio and Kalwar, {Imtiaz Hussain}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 ; Conference date: 14-11-2016 Through 16-11-2016",

year = "2017",

month = mar,

day = "27",

doi = "10.1109/ICAEES.2016.7888001",

language = "English",

series = "2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "17--20",

editor = "Rosdiadee Nordin and Mansor, {Mohd Fais} and Mahamod Ismail",

booktitle = "2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016",

}

Pathan, A, Memon, TD, Keerio, S & Kalwar, IH 2017, FPGA based performance analysis of multiplier policies for FIR filter. in R Nordin, MF Mansor & M Ismail (eds), 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016., 7888001, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016, Institute of Electrical and Electronics Engineers Inc., pp. 17-20, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016, Putrajaya, Malaysia, 14/11/16. https://doi.org/10.1109/ICAEES.2016.7888001

FPGA based performance analysis of multiplier policies for FIR filter. / Pathan, Aneela; Memon, Tayab D.; Keerio, Sharmeen et al.

2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. ed. / Rosdiadee Nordin; Mohd Fais Mansor; Mahamod Ismail. Institute of Electrical and Electronics Engineers Inc., 2017. p. 17-20 7888001 (2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FPGA based performance analysis of multiplier policies for FIR filter

AU - Pathan, Aneela

AU - Memon, Tayab D.

AU - Keerio, Sharmeen

AU - Kalwar, Imtiaz Hussain

PY - 2017/3/27

Y1 - 2017/3/27

N2 - In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.

AB - In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.

KW - Booth Algorithm

KW - FPGA

KW - Multiplier Policies

KW - Wallace Tree

UR - http://www.scopus.com/inward/record.url?scp=85018158967&partnerID=8YFLogxK

U2 - 10.1109/ICAEES.2016.7888001

DO - 10.1109/ICAEES.2016.7888001

M3 - Conference contribution

AN - SCOPUS:85018158967

T3 - 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016

SP - 17

EP - 20

BT - 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016

A2 - Nordin, Rosdiadee

A2 - Mansor, Mohd Fais

A2 - Ismail, Mahamod

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016

Y2 - 14 November 2016 through 16 November 2016

ER -

Pathan A, Memon TD, Keerio S, Kalwar IH. FPGA based performance analysis of multiplier policies for FIR filter. In Nordin R, Mansor MF, Ismail M, editors, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 17-20. 7888001. (2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016). doi: 10.1109/ICAEES.2016.7888001

FPGA based performance analysis of multiplier policies for FIR filter

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Keywords

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