FPGA based performance analysis of multiplier policies for FIR filter

Aneela Pathan, Tayab D. Memon, Sharmeen Keerio, Imtiaz Hussain Kalwar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Citations (Scopus)

Abstract

In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.

Original languageEnglish
Title of host publication2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
EditorsRosdiadee Nordin, Mohd Fais Mansor, Mahamod Ismail
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-20
Number of pages4
ISBN (Electronic)9781509028894
DOIs
Publication statusPublished - 27 Mar 2017
Externally publishedYes
Event2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 - Putrajaya, Malaysia
Duration: 14 Nov 201616 Nov 2016

Publication series

Name2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016

Conference

Conference2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
Country/TerritoryMalaysia
CityPutrajaya
Period14/11/1616/11/16

Keywords

  • Booth Algorithm
  • FPGA
  • Multiplier Policies
  • Wallace Tree

Fingerprint

Dive into the research topics of 'FPGA based performance analysis of multiplier policies for FIR filter'. Together they form a unique fingerprint.

Cite this