@inproceedings{da511af15035469db6de04cd714f5661,
title = "FPGA based performance analysis of multiplier policies for FIR filter",
abstract = "In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.",
keywords = "Booth Algorithm, FPGA, Multiplier Policies, Wallace Tree",
author = "Aneela Pathan and Memon, {Tayab D.} and Sharmeen Keerio and Kalwar, {Imtiaz Hussain}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 ; Conference date: 14-11-2016 Through 16-11-2016",
year = "2017",
month = mar,
day = "27",
doi = "10.1109/ICAEES.2016.7888001",
language = "English",
series = "2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "17--20",
editor = "Rosdiadee Nordin and Mansor, {Mohd Fais} and Mahamod Ismail",
booktitle = "2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016",
}