Fpga’s dual-port rom-based 8x8 multiplier for area optimized implementation of dsp systems

A. Pathan, T. Memon

Research output: Contribution to journalArticlepeer-review


FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core.

Original languageEnglish
Article number2011
JournalIranian Journal of Electrical and Electronic Engineering
Issue number4
Publication statusPublished - Dec 2021
Externally publishedYes


  • Block Memory
  • Digital Signal Processing
  • FPGA
  • Multiplier


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