Performance-area tradeoffs in the design of a short word length FIR filter

Tayab D. Memon, Paul Beckett, A. Z. Sadik

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)

Abstract

We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9dB at the cost of a doubling in hardware area.

Original languageEnglish
Title of host publication5th International Conference on MEMS NANO, and Smart Systems, ICMENS 2009
PublisherIEEE Computer Society
Pages67-71
Number of pages5
ISBN (Print)9780769539386
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 5th International Conference on MEMS NANO, and Smart Systems, ICMENS 2009 - Dubai, United Arab Emirates
Duration: 28 Dec 200930 Dec 2009

Publication series

Name5th International Conference on MEMS NANO, and Smart Systems, ICMENS 2009

Conference

Conference2009 5th International Conference on MEMS NANO, and Smart Systems, ICMENS 2009
Country/TerritoryUnited Arab Emirates
CityDubai
Period28/12/0930/12/09

Keywords

  • FPGA
  • Sigma delta modulation
  • SQNR
  • SWL filters

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