Reconfigurable blocks based on balanced ternary

Paul Beckett, Tayab Memon

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


Silicon-on-Insulator CMOS fabrication technologies are now available that offer a number of unique advantages including the availability of multiple simultaneous transistor thresholds. This paper proposes and analyzes a number of circuits for a reconfigurable array organization based on a balanced ternary logic system in which the logic set {-1, 0,+1} maps directly to equivalent voltage levels {-1V, 0V, +1V}. A number of low-power, high-speed components, such as a ternary buffer, flip-flop and look-up table, are described and simulated based on the characteristics of a commercially available silicon-on-sapphire process. A brief analysis indicates that the circuits will be capable of operating at the 22 nm technology node and beyond. A simple example of a Sigma-Delta Modulated FIR filter is mapped to the array and some preliminary estimates are made of its performance and area based on both 3-input and 4-input look-up tables. The simulated ternary array is shown to be capable of operating at clock speeds of more than 200 MHz such that it will readily support standard video bandwidths at useful over-sampling ratios.

Original languageEnglish
Pages (from-to)3-13
Number of pages11
JournalJournal of Signal Processing Systems
Issue number1
Publication statusPublished - Apr 2012
Externally publishedYes


  • Circuit design
  • Digital logic
  • FPGA
  • Short word length DSP
  • Silicon-on-sapphire
  • Ternary


Dive into the research topics of 'Reconfigurable blocks based on balanced ternary'. Together they form a unique fingerprint.

Cite this