In the recent past, a new set of digital signal processing algorithms are developed called short word length (SWL) DSP systems to mitigate the multiplier complexity that is an inherent part in most DSP functions. In SWL algorithms, the critical element is sigma-delta modulation (SDM). In this paper, we present the design, implementation, and hardware synthesis of the FIR filter and adaptive algorithms with the conventional and proposed multiplier schemes. Two proposed short word length adaptive algorithms namely Wiener and Steepest-Descent are compared with their counterpart LMS algorithm using conventional and proposed multiplier schemes. The hardware synthesize of these algorithms is done using Xilinx Spartan-6 and Vertex-7 FPGA and comparison is done based on area-performance-power. The overall results show that the sigma-delta modulation based adaptive DSP algorithm outperforms and is an efficient approach for mobile communication.
- Short word length
- Sigma-delta modulation
- Single-bit adaptive channel equalizer