Single-bit ternary FIR filter in FPGA Using canonical signed digit encoding

Tayab D. Memon, Abdullah Alhassani, Paul Beckett

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)


Sigma-delta modulation based single-bit ternary DSP algorithms have been extensively studied in the literature. More recently, FPGA based design and analysis of ternary FIR filter with distributed arithmetic (DA) algorithm have been reported in comparison equivalent multi-bit systems. In this paper, we present the design and synthesis of single-bit ternary and multi-bit (i.e., conventional) FIR filters using a more complex but efficient encoding technique called canonical signed digit (CSD) in both pipelined and non-pipelined modes. Both filter types are coded into VHDL and synthesized using small commercial FPGA devices in Quartus-II. Synthesis results show that in pipelined mode single-bit ternary FIR filter offers approximately 90% better clock performance than multi-bit FIR filter. Single-bit ternary FIR filter achieved clock frequency of 370 MHz using Stratix-III device that can easily process a 6-MHz video signal transmission. The single-bit DSP systems are highly beneficial for mobile communication purpose.

Original languageEnglish
Title of host publicationEmerging Trends and Applications in Information Communication Technologies - Second International Multi Topic Conference, IMTIC 2012, Proceedings
Number of pages9
Publication statusPublished - 2012
Externally publishedYes
Event2nd International Multi Topic Conference, IMTIC 2012 - Jamshoro, Pakistan
Duration: 28 Mar 201230 Mar 2012

Publication series

NameCommunications in Computer and Information Science
Volume281 CCIS
ISSN (Print)1865-0929


Conference2nd International Multi Topic Conference, IMTIC 2012


  • CSD Encoding
  • FPGA Implementation
  • Sigma-delta Modulation
  • Ternary FIR-like Filter
  • VHDL


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