Sigma-delta modulation based single-bit ternary DSP algorithms have been extensively studied in the literature. More recently, FPGA based design and analysis of ternary FIR filter with distributed arithmetic (DA) algorithm have been reported in comparison equivalent multi-bit systems. In this paper, we present the design and synthesis of single-bit ternary and multi-bit (i.e., conventional) FIR filters using a more complex but efficient encoding technique called canonical signed digit (CSD) in both pipelined and non-pipelined modes. Both filter types are coded into VHDL and synthesized using small commercial FPGA devices in Quartus-II. Synthesis results show that in pipelined mode single-bit ternary FIR filter offers approximately 90% better clock performance than multi-bit FIR filter. Single-bit ternary FIR filter achieved clock frequency of 370 MHz using Stratix-III device that can easily process a 6-MHz video signal transmission. The single-bit DSP systems are highly beneficial for mobile communication purpose.