SWL algorithms optimization using alternative adder module in FPGA

Tayab D. Memon, Shaji Farooq Baig, Marvi Deshi, Imtiaz Hussain Kalwar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF dominates upon multi-bit filter overall. In this work, we have adopted ternary sigma-delta modulated arithmetic adder (i.e., improved ternary adder (ITA)) and simulated it in ModelSim for functional verification. Further, it is synthesized in Xilinx for chip cost and its maximum performance measured in (FMAX) compared to conventional adder module used in SBTFF. The synthesize results show that ITA performs excellent while inputs are higher than 64 with lower chip areas, whereas its performance is poor at lower inputs compared to conventional adder. These results enhance the usefulness of existing short word length DSP algorithms for fast and efficient mobile communication.

Original languageEnglish
Title of host publication2017 6th Mediterranean Conference on Embedded Computing, MECO 2017 - Including ECYPS 2017, Proceedings
EditorsRadovan Stojanovic, Lech Jozwiak, Budimir Lutovac, Hana Kubatova
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509067411
DOIs
Publication statusPublished - 12 Jul 2017
Externally publishedYes
Event6th Mediterranean Conference on Embedded Computing, MECO 2017 - Bar, Montenegro
Duration: 11 Jun 201715 Jun 2017

Publication series

Name2017 6th Mediterranean Conference on Embedded Computing, MECO 2017 - Including ECYPS 2017, Proceedings

Conference

Conference6th Mediterranean Conference on Embedded Computing, MECO 2017
Country/TerritoryMontenegro
CityBar
Period11/06/1715/06/17

Keywords

  • alternative adder module
  • FGGA
  • introduction
  • short word length (SWL)
  • ternary adder

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